1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method thereof.
2. Description of Related Art
In recent years, chip scale packages (CSPs) have been developed to meet the demand for lighter, thinner and smaller semiconductor packages. Such a chip scale package has a size the same as or slightly larger than that of a chip. FIGS. 1A to 1D are cross-sectional views showing a fabrication method of a conventional chip scale package as disclosed by U.S. Pat. No. 7,202,107.
Referring to FIG. 1A, a carrier board 10 having a heat-sensitive adhesive layer 100 is provided. A plurality of chips 11 each having an active surface 11a with a plurality of electrode pads 110 and an inactive surface 11b opposite to the active surface 11a is disposed on the carrier board 10 and attached to the adhesive layer 100 through the active surfaces 11a thereof.
Referring to FIG. 1B, an encapsulant 12 is formed on the adhesive layer 100 to encapsulate the chips 11, wherein the encapsulant 12 has a first surface 12a attached to the adhesive layer 100 and an exposed second surface 12b. 
Referring to FIG. 1C, the chips 11 and the encapsulant 12 are heated so as to be completely separated from the heat-sensitive adhesive layer 100, thereby exposing the active surfaces 11a of the chips 11 and the first surface 12a of the encapsulant 12.
Referring to FIG. 1D, a wiring layer 13 is formed on the active surfaces 11a of the chips 11 and the first surface 12a of the encapsulant 12, and then a singulation process is performed along predefined cutting lines L to obtain a plurality of chip scale packages without substrates.
However, in the fabrication process of FIG. 1C, after the chips 11 and the encapsulant 12 are completely separated from the adhesive layer 100, the overall package structure loses the rigid support of the carrier board 10 such that warpage can easily occur to the backside of the overall package structure (as shown by the dashed lines in FIG. 1C), and, even worse, cracking of the chips 11 may occur.
Further, if a wiring process is performed to the backside of the package, warpage can occur on the front side of the structure. The above-described front and back warpage effects cannot completely offset each another, thus reducing the reliability of subsequent processes and reducing the product yield.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.